The present invention relates to a method and/or architecture for converting high-frequency serial data to lower frequency parallel data generally and, more particularly, to a method and/or architecture for using a recovered data-encoded clock to convert high-frequency serial data to lower frequency parallel data.
Refering to FIG. 1, a circuit 10 illustrating a conventional serial to parallel converter is shown. The circuit 10 has an exclusive OR gate 12, a flip-flop 14, a flip-flop 16, a flip-flop 18, a flip-flop 20, a flip-flop 22, a flip-flop 24, a multiplexer 26, a shift register 28 and an asynchronous FIFO memory 30. The circuit 10 converts an incoming serial data stream into a parallel data stream in response to a strobe signal and a high-speed system clock signal.
The circuit 10 relies on the shift register 28 that is loaded serially to transfer parallel data into the FIFO storage block 30. The shift register 28 is continuously shifted in response to the high-speed system clock. The data in the shift register 28 is loaded into the FIFO 30 when a binary counter (not shown) reaches a predetermined word width (e.g., 2, 4 or 8).
The circuit 10 can mis-align data when the word width of the serial data stream is less than the FIFO width, or when there is an incomplete word at the end of the serial data stream. Incomplete words can occur regularly when dribble bits are sent (see IEEE 1394 standard).
The circuit 10 requires an external high-speed clock source. Synchronizing the high-speed clock with the data clock can require a complex clocking scheme.
The present invention concerns an apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for using a recovered data-encoded clock to convert high-frequency serial data to lower frequency parallel data that may: (i) maintain an order of the incoming data without realigning incomplete words externally to a storage device; (ii) implement gray codes to directly access the memory and transfer pointer information across clock domains; (iii) guarantee that data is always valid when clocked as the clock is generated directly from the data; (iv) eliminate the need for a complex clocking scheme and external high-speed clock source; (v) run completely on the recovered data clock, even though the recovered data clock is not continuous; (vi) automatically maintain proper order and alignment of incoming data regardless of width; (vii) automatically strip xe2x80x9cdribble bitsxe2x80x9d from the end of the data stream if desired; and/or (viii) be synchronous and synthesizable, minimizing errors and reducing time-to-market.